1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a semiconductor integrated circuit including a delay locked loop (DLL) and a method for driving the same.
2. Description of the Related Art
In general, a semiconductor integrated circuit such as DDR SDRAM (Double Data Rate Synchronous DRAM) includes a DLL configured to equalize the phases of an internal clock signal and an external clock, in order to compensate for time delay caused by an internal circuit when the external clock signal inputted from outside is used inside. More specifically, the DLL receives an external clock signal, compensates for delay components in an actual clock path and data path, and applies negative delay in advance such that data outputted from the semiconductor integrated circuit may be synchronized with the external clock signal.
FIG. 1 is a block configuration diagram of a conventional semiconductor integrated circuit.
Referring to FIG. 1, the conventional semiconductor integrated circuit 100 includes an input buffer 110, a DLL 120, and an output driver 130. The input buffer 110 is configured to generate an internal clock signal ICLK corresponding to an external clock signal ECLK inputted through a first pad PAD1. The DLL 120 is configured to generate a DLL clock signal DLLCLK corresponding to the internal clock signal ICLK. The output driver 130 is configured to output data SYNC_DATA synchronized with the DLL clock signal DLLCLK to a second pad PAD2.
FIG. 2 is an internal configuration diagram of the DLL 120 illustrated in FIG. 1.
Referring to FIG. 2, the DLL 120 includes a delay line 121, a replica delay 123, a phase comparator 125, and a control signal generator 127. The delay line 121 is configured to delay the internal clock signal ICLK by a delay time for locking the clock signal in response to a delay control signal CTRL_DELY and output the DLL clock signal DLLCLK. The replica delay 123 is configured to delay the DLL clock signal DLLCLK by a delay time D3 equal to an actual delay through a clock path and data path and output a feedback clock signal FBCLK. The phase comparator 125 is configured to compare the phases of the internal clock signal ICLK and the feedback clock signal FBCLK to output a comparison signal UP/DN. The control signal generator 127 is configured to generate the delay control signal CTRL_DELY in response to the comparison signal UP/DN.
Here, the delay time D3 equal to the actual delay through the clock path and data path is typically referred to as a replica delay time. The modeled delay time D3 is defined as the sum of a delay time D1 equal to an actual delay through a path until the internal clock signal ICLK is generated from the first pad PAD1 receiving the external clock signal ECLK and a delay time D2 equal to an actual delay through a path until the data SYNC_DATA synchronized with the DLL clock signal DLLCLK is outputted to the second pad PAD2 (D3=D1+D2).
Hereinafter, an operation of the semiconductor integrated circuit 100 configured in such a manner will be described.
During initial driving, when the external clock signal ECLK is buffered through the input buffer unit 110 and transmitted as the internal clock signal ICLK to the delay line 121, the delay line 121 bypasses the internal clock signal ICLK.
Subsequently, the replica delay 123 delays the DLL clock signal DLLCLK outputted from the delay line 121 by the replica delay time D3 and outputs the delayed DLL clock signal to the phase comparator 125.
The phase comparator 125 compares the phase of the internal clock signal ICLK outputted form the input buffer unit 110 with that of the feedback clock signal FBCLK outputted from the replica delay 123. The control signal generator 127 generates the delay control signal CTRL_DELY in response to the comparison signal UP/DN outputted from the phase comparator 125 and outputs the delay control signal CTRL_DELY to the delay line 121.
Accordingly, the delay line 121 delays the internal clock signal ICLK by a desired delay time in response to the delay control signal CTRL_DELY and outputs the DLL clock signal DLLCLK.
When the above-described series of operations are repeated and the phases of the internal clock signal ICLK and the feedback clock signal FBCLK are synchronized with each other as the comparison result of the phase comparator 125, a first delay time of the delay line 121 is locked. This is shown in FIG. 3.
Referring to FIG. 3, it can be seen that the internal clock signal ICLK and the feedback clock signal FBCLK are synchronized with each other. At this time, the DLL clock signal DLLCLK is delayed by the first delay time (N*tCK−D3) for locking, compared with the internal clock signal ICLK.
Meanwhile, after the first delay time (N*tCK−D3) for obtaining a lock the delay line 121 is decided, that is, after a tracking process is completed, an update process is performed at each desired period. The update process is performed to compensate for a jitter which may occur in the DLL clock signal DLLCLK due to noise or the like. The update process is performed by repeating the above-described tracking process.
The semiconductor integrated circuit 100 may exhibit stable operation performance because output data is synchronized with the external clock signal ECLK.
However, the semiconductor integrated circuit 100 configured in such a manner also has the following features.
The DLL 120 included in the semiconductor integrated circuit 100 may perform the update process using a desired update period, after the tracking process is completed. Here, the DLL 120 may not generate a stable DLL clock signal DLLCLK for each different operation environment. For example, in a low-VDD and high frequency environment, the update period may be faster than the delay time occurring in the loop path of the DLL 120, which includes the delay line 121, the replica delay 123, the phase comparator 125, and the control signal generator 127. Accordingly, a jitter occurs in the DLL clock signal DLLCLK. Furthermore, in a high-VDD and low-frequency environment, the update period may be slower than the delay time occurring in the loop path of the DLL 120. Accordingly, tracking speed may not be optimized during the update process. According to an example, the delay time occurring in the loop path of the DLL 120 changes according to an operation frequency or PVT (process, voltage, and temperature) condition. Here, optimizing the update period of the DLL 120 is useful.